This invention relates to a parallel multiplier comprising a plurality of full-adding circuits interconnected in a systolic array.
Parallel multipliers can perform high-speed multiplication in large-scale integrated (LSI) or very-large-scale integrated (VLSI) microprocessors, digital signal processors, and other types of digital circuits. A parallel multiplier comprises a plurality of unit circuits having full-adding circuits, each of which multiplies a single pair of bits. The unit circuits are organized into stages that generate partial products. Each stage adds its partial product to the sum of the partial products in the previous stages and supplies the result to the next stage, causing the addition of partial products to "ripple" rapidly through the array and the final product to be produced at the end. In other words, the operation "progresses" or "propagates" from the first stage to the final stage and the intermediate results of the calculation appear at short intervals in sequence at the outputs of the first through the final stages.
A problem of prior-art parallel multipliers of this design is their high power consumption.